LAPPD Figures for Papers and Talks

Fulldemountablepicture unsealed%202

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The Demountable Tile, unsealed. This is a proto-type test Tile consisting of real parts, with the exception of the cathode, which is Aluminum, and the Top Seal, which is by an O-ring and retainer. The purpose is to test the no-pin `Look Ma No-Hands' internal HV circuit and also the pulsed performance of the complete stack of 2 MCP's, 3 ALD-functionalized spacers, and the 50-ohm transmission line anode. The anode strips are read out in this implementation via SMA connectors at each end of the strips on the Fan-Out Card.

Avgpulseshapes

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Pulses from the Demountable's first pump-down, demonstrating the first test of the no-pin `Look Ma No-Hands' internal voltage divider scheme. The stack consists of 2 MCP's separated by ALD-functionalized spacers. The 2 plates were measured to have resistances of 8 and 10 Megs. The spacers were ALD'd with the target voltages of 200, 200, and 450 Volts at 100-microamps. The pulse shapes are from an average of 1000 pulses vs HV voltage; the average noise from the Pokels cell has been subtracted.

Richn frugaltileprogress

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The evolution of the 8''-square tile from conceptual drawing (Left) to realized glass parts (Right). In both drawings the layers of window (top), spacers and MCP-plates (middle), and RF-transmission-line anode (bottom) have been separated vertically to demonstrate the structure.
Courtesy of Rich Northrop

Dsc 3513

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The front side of the Supermodule, which holds twelve tiles in three rows of four tiles each, sitting on the Tray. Three tiles have been left off so that the strip-line copper ground plane is visible. The Analog Cards are visible on the ends of the tile rows.
(Photo credit: Rich Northrop)

Dsc 3536

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The back side of the Supermodule, showing the Digital Cards connected to the Analog Cards and to the Central Card (CC). The CC
transmits the time, location, and integrated charge of hits to a PCI-E computer containing a teraflop GPU for real-time reconstruction and display.
(Photo-credit Rich Northrop)

Lappd sumoassembly3

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A conceptual drawing of the SuperModule, which consists of twelve tiles in three rows of four tiles each, sitting on the
Tray. The Tray comprises the strip-line ground plane (copper), the Analog Cards (AC) that support the 6-channel 10-15 GHz sampling chips, the Digital Cards (DC) that extract time and charge from the
digital output of the AC, and the Central Card that forms hits with time, position, and charge from the DC's at each end of a tile-row.
(Credit: Rich Northrop).

Eric scope psec anode v2

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A simultaneous display of a fast pulse digitized on a Tektronix scope (price at time of purchase \$142,000) and the PSEC-4
ASIC. (Courtesy Eric Oberla)

Erico psec4 performance slide

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A summary of the PSEC-4 ASIC performance.
(Courtesy of Eric Oberla)

Erico psec4 performance2 slide

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Performance of the PSEC-4 ASIC on 10 and 13.3 GHZ sine-waves.
(Courtesy Eric Oberla)

Erico 2012 03 01 8inchmcp event0

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The pulses from a pair of 8'' ALD-functionalized MCP's, measured at the 2 ends of an 8'' glass tile anode strip. The signal is created using the fast (10's of fsec) laser at the Argonne Advanced Photon Source and an aluminum photocathode.
(From Eric Oberla's March 6, 2012 Blog post).